Setting 100 MHz on Stratix IV GX

Hi,

When using designs with clocks in them, you have two steps involved:

1. Assign the clock to respective clock pin via Pin Planner / Assignment editor. If the clock is a single-ended one , you can connect it to any of the CLKn/CLKp pins on the device.
2. Add a SDC (Synopsys Design Constraints) file to the project which will mention the clocks , delays, etc. In the SDC you will mention the clock period aka Frequency of operation and have the tool look for the associated clock in the design and apply to it.
3. Also mention the input and output delays, false-paths and multi-cycle paths if any.

all of these put together will ensure that your design works as it should for that required frequency/timing requirements.

Examples of SDC file:

#**************************************************************
# Time Information
#**************************************************************
 
set_time_format -unit ns -decimal_places 3
 
 
 
#**************************************************************
# Create Clock
#**************************************************************
 
create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]
create_clock -name {sys_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_Clk_50Mhz}]
create_clock -name {vClk} -period 20.000 -waveform { 0.000 10.000 } 
 
#**************************************************************
# Clock Uncertainity
#**************************************************************
derive_clock_uncertainty
 
#**************************************************************
# Input Delay
#**************************************************************
set_input_delay -clock { vClk } 0.0 [get_ports {FPGA_Clk_50Mhz FPGA_reset}]
set_input_delay -clock { vClk } 0.0 [get_ports {altera_reserved_tck altera_reserved_tdi altera_reserved_tms}]
 
 
#**************************************************************
# Output Delay
#**************************************************************
set_output_delay -clock { vClk } 0.0 [get_ports timer_out]
set_output_delay -clock { vClk } 0.0 [get_ports altera_reserved_tdo]