Hi,
Kindly find the inline answers.
What do I need to do (hopefully in verilog since that's my only source) to try a higher clock speed
>> Can get lot of codes from the google . Appending a simple program
module frequency_divider_by2 ( clk ,rst,out_clk );
output reg out_clk;
input clk ;
input rst;
always @(posedge clk)
begin
if (~rst)
out_clk <= 1'b0;
else
out_clk <= ~out_clk;
end
endmodule
ii) How do I get around this "differential clock output" problem
In Quartus ,Open the pin planner change the I/O standard to LVDS
iii) How do I tell Quartus II that the signal in question is a clock. I noticed when it compiled it squawked about "no clock" but then later in the compile noticed that my signal called "clk" was connected to pin AC34 which it knew was a clock and it said something about "promoting" my clk to a "clock".
>> Connect to the specific dedicated clock pins .
Hope it clarifies
New Contributor
