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Altera_Forum's avatar
Altera_Forum
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16 years ago

Send on a 8 data bus : 8 data and 8 data and ...

Hi,

My problem is very simple :

I want to send on a single bus of 8 bits (named "BigBus" for example), 3 differents letter (coded in ASCII so 8 bits each).

At each clock count, the data must change :

BigBus = Letter 1 (Wait rising_edge clock) Letter 2 (wait rising_edge clock) Letter 3 (Wait rising_edge clock) Letter 1 (Wait rising_edge clock) Letter 2 ...

I know that what I shearch is a multiplexer but every example I have are not easy to write in vhdl and furthermore, I want to add a new letter quickly (in fact, if it's possible, I just want to add a line for each letter added).

Thanks for your help and sorry pour my bad english, I'm French...:rolleyes:

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    use counter and case, or 2D array: 

    
type my_data is array(0 to 2) of std_logic_vector(7 downto 0);
signal my_characters: my_data := ("01110100","00001111","00110000");
 
-- or
--constant my_characters: my_data := ("01110100","00001111","00110000");
 
signal count: integer range 0 to 2;
 
begin
 
process
begin
wait until clk = '1';
 
if count = 2 then
    count <= 0;
else
    count <= count + 1;
end if;
 
bigbus <= my_characters(count);
 
end process;