Forum Discussion

New Contributor

6 years ago

S10-DX-Kit and reference DMA over PCIe design

hello i have s10-DX kit which I am planning on using for developing a design. for this design i intend to get DMA over PCIe as basic functionality; and i will develop my user logic on top of it. ...

BoonT_Intel

Frequent Contributor

6 years ago

Hi Sir,

You may generate the design directly from quartus. Then follow the steps using this document.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-ptile-pcie-avmm.pdf

This document complete describe the step to generate the design. Also the step to run it on the s10 dx dev kit.

Forum Discussion

S10-DX-Kit and reference DMA over PCIe design

Recent Discussions

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work

PCIe Root Complex on DK-A5E013BM16AEA