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Altera_Forum
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16 years ago

Running Triple Speed Ethernet Design on Cyclone III Development Board

I am attempting to run the Simple Socket Server example code on a Cyclone III Development Board. The design compiles in Quartus 9.1 and I can program the board.

I generated an app and bsp for the Simple Socket Server example using Nios II 9.1 Software Build Tools for Eclipse. I selected the correct SOPC information file. The project compiles, and I can run it on the target hardware.

Everything seems to run okay, but I cannot connect to the device. Using a packet sniffer, I can see my PC generating ARP packets; however, the target never generates any packets in response at all. The link_1000 and DUPLEX LEDs are both illuminated. The RX LED blinks when the ARPs go out from the PC, also.

I noticed the following comment in the readme file for the design:

- The 3c120 development kit board is using RGMII interface for the PHY connection,

the TSE initialization need to updated to turn on the timing control on the

Marvell PHY. Please refer to the simple_socket_server_tse_3c120_rgmii and

web_server_tse_3c120_rgmii for the details.

I suspect this may have something to do with the problem, but I am not sure.

Can anybody tell me what I need to do to get this running?

Additional Information:

The console output is as follows:

=============== Software License Reminder ================

This software project uses an unlicensed version of the NicheStack TCP/IP

Network Stack - Nios II Edition. If you want to ship resulting object

code in your product, you must purchase a license for this software from

Altera. For information go to: "http://www.altera.com/nichestack"

=====================================================

InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.

prep_tse_mac 0

Your Ethernet MAC address is 00:07:ed:ff:22:2e

prepped 1 interface, initializing...

[tse_mac_init]

INFO : TSE MAC 0 found at address 0x08004000

INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0]

INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

INFO : PHY[0.0] - Auto-Negotiation PASSED

INFO : PHY[0.0] - Checking link...

INFO : PHY[0.0] - Link established

INFO : PHY[0.0] - Speed = 1000, Duplex = Full

OK, x=1, CMD_CONFIG=0x00000000

MAC post-initialization: CMD_CONFIG=0x0400020b

[tse_sgdma_read_init] RX descriptor chain desc (1 de

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Slacker,

    Your suggestion did the trick. Thank you so much. Your "Guru" title is well deserved.

    --Steve
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    hi slacker ,

    i had a problem

    im working on 1g link with rgmii mode ....i am using my own mac ,its working for 100Mbps ,but where as for RGMII i used separate code by using the ALTDDR_out,_in registers and im sending to pc ,,,,the linux what i m using its sending the packets ,,,the protocal is in such a way that it will send packets whenever its receive acknowledge ...my board is sending the ack nowledge ment packet that i taped in signaltap..but in wireshark i was not able to capture,,,,

    and picture is not completed

    reply as soon as possible
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If the packet is malformed (wrong header, bad CRC) it may be dropped by the network card on your PC or by the linux driver before you have a chance to see it in wireshark. Some interfaces have statistics saying if some bad packets were dropped. You should check if this counter is increasing. I think that you can see these statistics counters with ifconfig.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    hi daixiwen can u suggest me im new to linux can u tell me what and all the commands i need to type in linux to see the statistics

    im using arriaiigx board ep2agx260i3 i tried with all options now im asking what i need to do ....im not using the megacores im using only iddr,oddr thats all ......i did 180deg phase to rxclk thenonly i saw the 1 packet of thae picture...after wards im not able to see the next packets ...and also tx packests send by board was not able to capture by the wireshark
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I'm not very familiar with all those commands, but a man ifconfig should give you some details I think.

    Does the LED on your PC's network card blink when you send a packet?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    yes when i send a packet the ethernet tx rx leds are glowing ......tx,rx leds are present on my board and the leds on the network cards also blinking

    wn i config my board with 1g link the led present in the board is glowing...that indicated that my link was proper the problem is wn im transmitting a acknowelge ment packet ...
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    I'm not very familiar with all those commands, but a man ifconfig should give you some details I think.

    Does the LED on your PC's network card blink when you send a packet?

    --- Quote End ---

    if config is will tell what is the ipaddress and its showing the details like

    dropped:0 loss - 0% loss transmission packets ,received packets ...

    for me transmission packets is equal to the received packets
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You could try to loopback your transmitted packets right back to your receive interface on your board, without connecting it to a PC. That way you should know if the PHY chip gets your data to transmit correctly.

    If you have access to the PHY's MDIO registers, you should be able to configure it in loopback mode to do just that, or an alternative method is to do a wire yourself that connects the rx and tx pairs together.