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Altera_Forum's avatar
Altera_Forum
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10 years ago

Run / Debug problems with NIOS on Cyclone V SoC Dev Board

Hi all,

i want to build a system with a Nios Core and the software will run on the hps ram. My first step i built the system with nios core and with fpga ram. I test my software with "Nios for eclipse" with the Tool "Run as -> NIOS II Hardware". Which rans.

My next step i changed the fpga ram to hps ram but if i want to debug or to run the software in "NIOS for eclipse" i get the error:

Using cable "USB-BlasterII [USB-1]", device 1, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused

I use Quartus 14.1

My QSYS Build

http://www.alteraforum.com/forum/attachment.php?attachmentid=11147&stc=1

I think i have problems with the Ram Timings but i didnt find any descriptions about the settings for this dev board Cyclone V SoC.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    I wouldn't recommend doing this. Memory contention will slow down the HPS significantly. It's much better to use on-chip ram or a separate ram chip for the NIOS. The added cost for extra ram chip(s) isn't much considering the cost of the SoC itself.