Forum Discussion

YigalB1's avatar
YigalB1
Icon for New Contributor rankNew Contributor
1 year ago
Solved

RESERVED_INPUT_WITH_WEAK_PULLUP pins in DE1- Lite

I would like to use 3 pins of the 40 pin connector of the DE10-Lite for UART implementation (Tx,Rx,GND). At first I was thinking of using V10 & V9 because they are top left on the connector, so easy...
Fpga Devkit
  • FvM's avatar
    FvM
    1 year ago

    Hi,

    according to DE10-Lite schematic, all GPIO connector pins are connected to RX/TX capable pins in 3.3V IO banks, also questioned GPIO_7 and GPIO_9. I presume, you are seeing "RESERVED_INPUT_WITH_WEAK_PULLUP" in the .pin file of a specific project. It reflects the pin assignments of the design, not the capabilities of the FPGA. "Reserved input" is the assignment of an unused pin. You need to assign intended pins to top level signals in Pin Planner tool or Assignment Editor.

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.