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2 years ago

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Request of AXI bridge example for CycloneVsoc HPS to FPGA communication

Hi I've tried the AVALON MM bridge HPS to FPGA translating 32 bit data for each using alt_write_word() and alt_read_word(). There is ~2us latency between orders(128bit wide H2F bridge with 50MHZ cl...

tehjingy_Altera
2 years ago
Hi Alex

The dword read is the maximum size that is available by the library to read through the bridge.
Is reading using the dword improve the situation on your end?

The difference between a normal and burst command is the in the burst command there are addtional signals such as ARBURST, ARSIZE ,RLAST.
In the burst command it will have state the number of burst read from the receiver to send the data.
https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/AXI-Burst-Transfers

Regards
Jingyang, Teh

tehjingy_Altera

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Regular Contributor

2 years ago

Hi Alex

I see that the flow of data is from the FPGA to the HPS.

There is this example of moving data through the FPGA to HPS bridge instead of the HPS to FPGA bridge.

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/fpga-to-hps-bridges-design-example.html

It uses the SGDMA example. You might want to take a look at the cacheable route.

It uses the SGDMA IP to pass data from the FPGA fabric to the HPS memory location.

Then from the HPS you could access the data directly from the memory location.

Regards

Jingyang, Teh

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Contributor

2 years ago

Hi

Thnak you for your example, I'll check it soon.

The other question might be :

If Im going to burst transfer a 64bit buffer, what should I do on HPS side?

Is that just alt_write_dword() with at least 64 bit wide H2F AXI Master?

If so then what is the difference of burst transfer like that and normal transfer?

Thank you .

Reguards

Alex