Regarding the Intel Agilex series GPIO Banks IO standards

Hello,

I have gone through the ADC datasheet, in which my LVDS output offset voltage( VOS) range is 1.15 to 1.35 V. So, in order to fall the ADC output range in intel agilex series FPGA GPIO bank IO standard, I need to use the GPIO Bank VCCIO_PIO at 1.5 V, right?

I have checked in the reference schematic, in which by default GPIO Bank is operating with VCCIO_PIO at 1.2 V. In order to provide VCCIO_PIO at 1.5 V , Is there any software configuration need to operate these GPIO bank with VCCIO_PIO at 1.5 V?

Awaited your response.