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Maitry's avatar
Maitry
Icon for New Contributor rankNew Contributor
1 year ago

Regarding Ethernet /Transceiver tool kit error in F tile 10G Hard IP for AGFB027R24C FPGA device

Hello support team, We are using AGFB027R24C2I3E Agilex F series FPGA in our custom board. With Bank 13 A, 156.25 MHz (i_refclk2pll_clk) clock is interfaced ( CH6 = CJ7, CH8). And Tx, Rx is in CH1....
Fpga Devkit
paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi,


Good day to you.

May I know if the reset signals have been deasserted or not? This is because rx_pcs_ready deasserts when i_rx_rst_n/i_rst_n signal asserts or during the auto-negotiation and link training operation.


And also I would suggest you to try to generate design example using board type = Agilex devkit and compare the pin assignments to ensure the pin connections is same as devkit.


Regards,

Pavee