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Maitry's avatar
Maitry
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1 year ago

Regarding Ethernet /Transceiver tool kit error in F tile 10G Hard IP for AGFB027R24C FPGA device

Hello support team, We are using AGFB027R24C2I3E Agilex F series FPGA in our custom board. With Bank 13 A, 156.25 MHz (i_refclk2pll_clk) clock is interfaced ( CH6 = CJ7, CH8). And Tx, Rx is in CH1....
Fpga Devkit
Maitry's avatar
Maitry
Icon for New Contributor rankNew Contributor
1 year ago

Hello,

By changing CH6 to CH0 in the F tile 10G hard IP, My ethernet tool kit enabled. I have made a loopback. But after enable internal loopback and start reading all status, My Tx PLL lock status is = locked . but My Rx PCS ready status = not ready and Rx CDR locked status = Not locked.

What is the reason behind this above issue? Is there anything that we are missing over here?