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Nico77836's avatar
Nico77836
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6 years ago

Reference Design: AN690 and AN708 Gen2x4 AVMM DMA - Cyclone V : source code availability ?

Hello all,

I am looking for both hardware and software source files about the AN690 and AN708 Gen2x4 AVMM DMA - Cyclone V reference design.

However all pages end with broken links;

https://www.intel.com/content/www/us/en/programmable/documentation/nik1412548086590.html#nik1412548072360?erpm_id=6542115

https://forums.intel.com/s/createarticlepage?articleid=a3g0P0000005RPAQA2&artTopicId=0TO0P000000MWKBWA4&action=view

In the Cyclone V GT FPGA Development Kit pages, I found the hardware design with the mSGDMA IP core but there is no Linux driver source code.

In the design store,

There is all the required design for Arria 10 GX but nothing for Cyclone V.

Is someone can provide a link to download these sources code please ?

Thank you !

3 Replies

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
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    6 years ago

    Hie,

    For Cyclone V AVMM_DMA example design, its available in Quartus in the following directory.

    <install_dir>/ip/altera/altera_pcie/altera_ pcie___hip_avmm/example_designs directory:

    Please refer to the User Guide specific to Cyclone V PCIe AVMM_DMA as following instead of AN690 and AN708. The information about Example Design for Cyclone V PCIe AVMM DMA is covered in Pg 1-9.

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avmm.pdf

    Regards,

    Nathan

  • Nico77836's avatar
    Nico77836
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    6 years ago

    Hello Nathan,

    Thank you for your response.

    I already found the hardware example design (both in the Quartus install directory and on the cycloneVSX_5csxfc6df31_soc_v14.1b186.zip file available on the Cyclone V development kit page) , but I am also looking for the software part (Linux driver part), and I did not found anything.

    For example, there the content of the txt file avaiable on cycloneVSX_5csxfc6df31_soc_v14.1b186\examples\pcie\endport_example :

    !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

    !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

    No board re-work required

    on this test

    Do not change the PCIe clk setting

    Meaning, SoC devkit will provide

    the pcie clk to RP side

    !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

    !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

    This is tested on revC SoC board

    Tested with C5GX revC devkit.

    the root s/w expect the end port onchipmem to located at the address of 0x07000000

    Endport also have onchipmem on 0x08000000 as well.

    The example design uses mSGDMA on the RootPort side.

    Test start from RP->EP data transfer first.

    Then, send EP -> RP data transfer later.

    Data transfer size is 262144Byte, known long enough data size to ignore the over heads.

    With this settig, I've got this kind of performance.

    RP -> EP : 804.1720MB/s 262144Byte

    EP -> RP : 780.4692MB/s 262144Byte

    But there is obviously a Linux driver part, right ?

    Maybe do you have some knowledge about it ?

    Regards,

    Nicolas

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
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    6 years ago

    Hie Nicolas,

    I am afraid we don't provide the Linux driver part for this reference design. If it was provided, it will be mentioned in the user guide as I mentioned above.

    Regards,

    Nathan