New Contributor
New ContributorHello Nathan,
Thank you for your response.
I already found the hardware example design (both in the Quartus install directory and on the cycloneVSX_5csxfc6df31_soc_v14.1b186.zip file available on the Cyclone V development kit page) , but I am also looking for the software part (Linux driver part), and I did not found anything.
For example, there the content of the txt file avaiable on cycloneVSX_5csxfc6df31_soc_v14.1b186\examples\pcie\endport_example :
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
No board re-work required
on this test
Do not change the PCIe clk setting
Meaning, SoC devkit will provide
the pcie clk to RP side
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
This is tested on revC SoC board
Tested with C5GX revC devkit.
the root s/w expect the end port onchipmem to located at the address of 0x07000000
Endport also have onchipmem on 0x08000000 as well.
The example design uses mSGDMA on the RootPort side.
Test start from RP->EP data transfer first.
Then, send EP -> RP data transfer later.
Data transfer size is 262144Byte, known long enough data size to ignore the over heads.
With this settig, I've got this kind of performance.
RP -> EP : 804.1720MB/s 262144Byte
EP -> RP : 780.4692MB/s 262144Byte
But there is obviously a Linux driver part, right ?
Maybe do you have some knowledge about it ?
Regards,
Nicolas
