Altera_Forum
Honored Contributor
Honored ContributorRead then Write data on SRAM DE2 board
I am doing my final year project related to image processing. i write the image HEX file into DE2 SRAM board using DE2 control panel and trying to load the image data from each location of SRAM then process it. But i face the problem which read a data from location A then write the data into location B (copy the data from location A then overwrite the data on location B within 2 clock cycles of 50Mhz. But i get the result with all HIGH (0xFFFF) (which are not desired data i set for location A and B by using control panel before run my code) . But i get the undesired result by my vhdl code. Hope anyone help me fix this and would appreciate your help. :) Here is my code:
----------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity test1 is port(clock : in std_logic; LEDR: out std_logic_vector(15 downto 0); SRAM_ADDR: out std_logic_vector(17 downto 0); SRAM_DQ: inout std_logic_vector(15 downto 0); SRAM_CE_N: out std_logic; SRAM_OE_N: out std_logic; SRAM_WE_N: out std_logic; SRAM_UB_N: out std_logic; SRAM_LB_N: out std_logic ) ; end test1; architecture inside_top_level_entity of test1 is signal address: std_logic_vector(17 downto 0); signal data: std_logic_vector(15 downto 0); signal count:integer:=0; signal count_1Hz : integer:=0; shared variable twosam_add : integer:=1; type state_type is (s0, s1); signal state : state_type; begin SRAM_CE_N <= '0'; SRAM_UB_N <= '0'; SRAM_LB_N <= '0'; SRAM_OE_N <= '0'; process (clock) begin if clock'event and clock='1' then case state is -----read data from address 1 of SRAM when s0=> SRAM_DQ <= (others=>'Z'); SRAM_WE_N <= '0'; address <= conv_std_logic_vector(twosam_add,18); SRAM_ADDR <= address; data <= SRAM_DQ; state<=s1; -----write data to address 0 of SRAM when s1=> twosam_add:=0; address <= conv_std_logic_vector(twosam_add,18); SRAM_ADDR <= address; SRAM_WE_N <= '1'; SRAM_DQ <= data; end case; end if; end process; LEDR<=SRAM_DQ; end inside_top_level_entity;
