Forum Discussion
New ContributorStratix 10 1G/2.5G Ethernet reconfiguration not working in hardware
Hi dlim,
I finally managed to communicate with the PHY.
One problem was that some of the switches were not in the right position, so the pointer in the scripts was not pointing to the S10 FPGA.
Also a reset_n on the fw side was not negated (and so it was always in resetting all the time).
This is then solved.
A part for one register (for auto negotiation enabling) that I can't write.
But I would open a new ticket for that.
Thanks for your support.
Alessandra
Regular ContributorHi,
Sorry for the late reply.
Look like you are still facing some issue in accessing the Ethernet design via system console.
My suggestion is maybe you can try with simpler design to ensure you can get system console working correctly with your S10 MX dev kit first.
For S10 MX dev kit board, you just need to ensure you have configure all the board jumper setting back to default position.
For debugging system console, the connection mainly is relying on JTAG connection.
- You can try reduce JTAG frequency lower from 24MHz to either 16MHz or even 6MHz
- Also make sure you have provided correct reset sequence and clock frequency to the reconfig clock of your Ethernet IP design.
Thanks.
Regards,
dlim
New ContributorHi dlim,
I finally managed to communicate with the PHY.
One problem was that some of the switches were not in the right position, so the pointer in the scripts was not pointing to the S10 FPGA.
Also a reset_n on the fw side was not negated (and so it was always in resetting all the time).
This is then solved.
A part for one register (for auto negotiation enabling) that I can't write.
But I would open a new ticket for that.
Thanks for your support.
Alessandra
