Forum Discussion
New ContributorProper PERST# connection for FMC on Agilex5 Modular Development Kit
Whether the production Modular Development Kit already has PERST# physically routed from the PCIe edge connector to one of those HVIO pins, or whether you need a board-level modification, is a question specific to that board's schematic. I'd recommend checking the production board schematic (available from the kit webpage) to confirm whether that trace is already present before reaching for a soldering iron. If the board is used in PCIe slot mode, the nPERST line from the slot should reach the board; if it's used in tabletop/standalone mode, you may need to drive that pin from another source (e.g., an on-board logic signal or manual connection).
New ContributorI was able to get the PCIe link running through FMC. Here are the details so it can help others:
- PCIe link is set up as an endpoint
- Raw PERST from the link is connected to pin BF40 on the 3.3V HVIO bank through the pin 8 on the J23 header (carrier board).
- Internal to the FPGA: PERST is registered for timing and then brought out to pin CF121 on the 1.8V HVIO bank (carrier board net name MIPI_XTRIG0_1V8). This accomplishes the level shifting from 3.3V to 1.8V
- The actual PERST to the HIP is driven by the net MIPI_XHS0_1V8
- The connection between the two nets is accomplished by bridging pins 2 and 4 on the DIP switch S6 on the carrier card. I was able to use debug clips to establish a temporary connection before soldering the wire
Also, for the HIP clock connections I got the link working with either:
- using two clocks:
- AV120: connected to the refclk0 input on the HIP
- AY120: connected to the GTS PLL
- using a single clock:
- AV120: connected to both the HIP and the GTS PLL
Regular ContributorThank you for your sharing this information and it is good to know that you are able to get the PCIe link running through FMC.
