Forum Discussion
Occasional ContributorMSI with avalonMM-DMA ip
Hi,
I could not find the part that you have mentioned in the document. May I know which document you are referring to?
According to the PCI Local Bus Specification 2.3,
"If the Multiple Message Enable field (bits 6-4 of the Message Control register) is non-zero, the device is permitted to modify the low order bits of the message data to generate multiple messages."
Thanks
Best regards,
KhaiY
Regular ContributorHi,
1. Yes. You have to use this interface to receive information required to generate MSI interrupts to the Root Port via the TX Slave interface.
2. You have to design a Custom Interrupt Handler. You may refer to Figure 51 for an overview of the logic for the Custom Interrupt Handler. The Custom Interrupt Handler should include hardware to perform the following tasks:
- An MSI/MSI-X IRQ Avalon-MM Master port to drive MSI or MSI-X interrupts as
memory writes to the PCIe Avalon-MM bridge. - A legacy interrupt signal, IntxReq_i, to drive legacy interrupts from the MSI/
MSI-X IRQ module to the Hard IP for PCI Express. - An MSI/MSI-X Avalon-MM Slave port to receive interrupt control and status from
the PCIe Root Port. - An MSI-X table to store the MSI-X table entries. The PCIe Root Port sets up this
table.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf
Thanks
Best regards,
KhaiY
Occasional ContributorAs I've found in docs, the MSI vectors differ only in LSBits of data field. All of them use the same address.
Data field should be masked accordingly to count of vectors (2 - 0xFE, 4 - 0xFC, 8 - 0xF8 and so on) and then OR-ed with vector number.
Is it true?
