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JUNIOR's avatar
JUNIOR
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6 years ago

random adder(counter) error in FSM

Hi, I have random adder error in FSM problem the current result of reg [15:0]counter is : 1,2,3,4,5,4,5,6 but the correct result would be 1,2,3,4,5,6,7,8 Does anyone know how to fix this, any rep...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

I think you have to look at the toggling of GPIO_1[9] since that seems to be what's required to continue the count.

#iwork4intel

  • JUNIOR's avatar
    JUNIOR
    Icon for New Contributor rankNew Contributor
    6 years ago

    ​Thanks and I solve it by add one flip-flop to eliminate the glitch, replace GPIO with synchronized register

    always@(negedge CLOCK_50)

    begin

    REG_GPIO_1_9<= GPIO_1[9];

    end