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New Contributorrandom adder(counter) error in FSM
Hi,
I have random adder error in FSM problem
the current result of reg [15:0]counter is : 1,2,3,4,5,4,5,6
but the correct result would be 1,2,3,4,5,6,7,8
Does anyone know how to fix this, any reply is appreciated.
always@(negedge CLOCK_50)
begin
case(CS)
S0:
begin
if(GPIO_1[9]==1'b0)
begin
counter=counter+1;
CS=S1;
end
else
begin
CS=S0;
end
end
S1:
begin
if(GPIO_1[9]==1'b1)
begin
CS=S0;
end
else
begin
CS=S1;
end
end
endcase
end
2 Replies
sstrellSuper Contributor
I think you have to look at the toggling of GPIO_1[9] since that seems to be what's required to continue the count.
#iwork4intel
JUNIORThanks and I solve it by add one flip-flop to eliminate the glitch, replace GPIO with synchronized register
always@(negedge CLOCK_50)
begin
REG_GPIO_1_9<= GPIO_1[9];
end
