CAlex
Contributor
ContributorQuestions on CycloneVsoc example CV-FPGA-to-HPS-Bridge-design
Hi,
I'm using CycloneVsoc dev kit and want to use F2SDRAM function.
I followed the instruction of community and check the CV-FPGA-to-HPS-Bridge-design example you provided.
I have the following questions:
On platform designer:
1.The PLL output clk is 150Mhz.
Why Custom Rest Synchronizer input clock freq is not the same?
2. What does this IP do?
Ive read the verilog, but my only understanding is that it delay the reset signal for certern clk cycle.
3. How can I ensure the parameters of that IP are correct?
In ARMDS,
There is some codes about PRBS generater and checker, where can I get more information for these two parts?
For the example:
Can I use the HPS dma do the communication between FPGA and SDRAM?
Reguards
Alex
