Forum Discussion
New ContributorQuestion related to clock resource on Stratix V GX evaluation board
The high-speed clocks on the Stratix V GX Signal Integrity Kit—those running at 625 MHz, 644.53125 MHz..... —are tied strictly to the transceiver circuits. They aren’t usable for core logic, can’t feed the main PLLs, and won’t connect through something like ALTCLKCTRL. They’re simply not wired for general use in your design. If you need a clock for your logic, you’ll have to look elsewhere—like a lower-frequency on-board oscillator (often something like 50 MHz), or bring in your own via an HSMC port or SMA connector. Just make sure the pin you use can actually connect to the FPGA’s internal clock routing.
Super ContributorHave you downloaded the full kit installation? https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/v-gx-signal-integrity.html
The schematics would have all the detail you need.
- FvMAccording to reference manual, said clocks are connected exclusively as transceiver reference clocks, thus not available to feed core clock network and PLLs.
Steven06Hi FvM,
Thank you for your reply.
Can you please let me know which page in the manual this information is mentioned?
Thank you.
- Steven06
Thank you sstrell, I'll look into the schematics of the kit.
