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LSank's avatar
LSank
Icon for New Contributor rankNew Contributor
6 years ago

Query on Cyclone III FPGA LVDS IO and VCCIO

We are using the EP3C55 Cyclone III FPGA in our design. I have a query regarding the VCCIO for a bank when using LVDS IO. Here on Bank 1 and Bank 2, we have taken an LVDS clock output and connected ...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Siva,

Please find my response below:

1. I would like to know if there is an issue if we connect the VCCIO for these banks to 1.8V instead of 2.5V and still configure the clock IO as LVDS? If there is an issue, please let me know which specification gets violated and how it impact the LVDS Output /Clock input buffer?

VCCIO is a power rail for the I/O buffer. Having VCCIO 2.5V is important for LVDS to ensure that the LVDS output buffer can emit 2.5V output properly. Thus, it is recommended to have 2.5V VCCIO for LVDS.

2. Is there any workaround to enable using the LVDS Output and Clock input buffer in the Bank and still have the VCCIO at 1.8V?

Apologize that is no workaround for this. It would be better if you could have 2.5V Bank and 1.8V Bank separately.

Thank You.

Regards,

YL