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SamPF's avatar
SamPF
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1 year ago

quartus sythesize question

Hello, when I design a project, there are many modules in this project, in one of the modules (not the top module) I mark the wrong io type (for example: input tag to output), and in the module This...
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ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


In STP, I'm seeing b_EN high when using input PWRGD_a in Main_Seq.v. While seeing b_EN low when using output PWRGD_a in Main_Seq.v. I think the actual synthesis circuit result is the correct one because need input PWRGD_a to make b_EN high as b_EN depends on the if(PWRGD_a) begin.

However, I'm seeing same result (b_EN high) for both situation in simulation. I'll further confirm with the internal engineering team.


Thanks,

Regards,

Sheng


SamPF's avatar
SamPF
Icon for New Contributor rankNew Contributor
1 year ago

Hi ShengN

First of all thanks for your reply

You are right because this is a real problem we have in real systems, when we simulate everything is correct and we load to FPGA it does not work, so the synthesized circuit is correct, but how do I get this in simulation The problem is what we care about, so hopefully you can tell me what I can do in the simulation to prevent this problem, thanks.

BR,

Sam