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SamPF's avatar
SamPF
Icon for New Contributor rankNew Contributor
1 year ago

quartus sythesize question

Hello, when I design a project, there are many modules in this project, in one of the modules (not the top module) I mark the wrong io type (for example: input tag to output), and in the module This...
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sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

You're not seeing an issue because you have an intermediary wire, w_PWRGD_a, so you're never connecting the output of Main_Seq to top. The names can be the same in different levels of hierarchy.

As for why b_EN goes high in simulation and not in hardware, that's not as clear unless I put it into Quartus.