Occasional ContributorQuartus simulation differs from board results
Hi there!
Recently purchased board from Aliexpress with EPM570T100C5 in it
Just programmed simple overflow accumulator as used in old fractional N synthesizer schemes. Mine with registered ouput for overflow so is one clock delayed.
`timescale 1ns/1ps
`define clk_period 20
module testbench;
reg clk;
reg reset;
reg [3:0] prog;
wire [3:0] add;
wire clk9600;
wire overflow;
frac_acc uut(.clk(clk), .reset(reset), .clk9600(clk9600), .prog(prog), .overflow(overflow), .add(add));
initial clk = 1'b1;
always #(`clk_period/2) clk = ~clk;
initial begin
reset=1;
#105000
reset=0;
#20;
prog = 4'b0000;
#10;
prog = 4'b0001;
#380000
reset=1;
#440000
reset=0;
end
endmodule
Problem arrives when i program into board... Instead of each 16 cicles; above is true just for half cicles, as if adder was 3 bits not 4.
So if i want actual chip to behave as per image, i need to set add[4:0] and prog[4..0] and reprogramm it, and so on
Anyone has experiences such behavior?
besides above, seems if input pins are not tied to ground it doesnt read as 0, so need tie to gnd for propper operation, no sure if pull down resistor or pin type is in order here.
Thanks!
- clk9600 has most likely glitches in real hardware. Try to set in registered rather than combinational assignment.
