Quartus simulation differs from board results

Hi FvM

Yep, that did the trick

always @(posedge clk) begin
if (c>=5207)
c<=0;
else
c<=c+1;
clk9600 <= (c <= (5208/2)-1)? 1'b1:
1'b0;
end

The change added output through flip flop as per rtl netlist. so whatever glitch happened at logic it was stable after delayed clock. Its not first time i experience glitches, on this same design the carry propagation delay does a glitch, bigger chance when more adders in series, but after passing trough one clk delay it gives the room stabilize logic level so it is valid.

Im quite new on quartus and didnt see the glitches on real scope at first, and since simulation appeared fine i was a little puzzled.

I wish i know how to account for glitches at simulation level...

Thanks!