Quartus prime V19: .sdo files not generated for MAX V device, does it still support gate level simulation?

Found a misunderstanding in the setting, the manual says

2. Set up the simulation environment. To generate only a functional (rather than timing) gate-level netlist, click More EDA Netlist Writer Settings, and turn on Generate netlist for functional simulation only.

But in Quartus Prime 19.1, the option actually display as

Generate functional simulation netlist

This is very confuse people, if you turn on it as manual says, then .sdo file would not be generated

Turn off it you get .sdo file generated

Anyway thank Kenny to answer my question, hope Quartus could correct this confusion in next edition