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Occasional Contributor

4 years ago

Qsf file for emif ip arria 10 SoC development kit

Hi, Can anyone share the qsf file(pin assignment) for DDR4 EMIF IP using arria 10 SoC development kit(x72 fpga pin).

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Contributor

4 years ago

please refer to the attachment. change *txt to *qsf, could not attach qsf file.

ed_synth.txt9 KB

srinivasan
Occasional Contributor
4 years ago
Hi,

Thanks for sending the files...

Actually, arria 10 soc part number is 10s066N3F40E2SG...but in ed_synth.txt files they have mentioned 10s066N3f40I2SG...which i need to choose?

But in EMIF IP GUI i am selecting fpga development DDR4 HILO connector(x72)...If I select this , it automatically taking below part number...

arria 10 device:10s066N3f40I2SG
- yoichiK_altera
  Contributor
  4 years ago
  sorry ,attached wrong file. Here is the right one.
  ed_synth.txt9 KB
  - srinivasan
    Occasional Contributor
    4 years ago
    Hi,
    Ya got it..thanks..
    Which clock should I connect to signal tap analyser??
    Whether I need to connect pll_ref_clock or clk_50mhz