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weid's avatar
weid
Icon for New Contributor rankNew Contributor
6 years ago

Pull up or down of DCLK and DATA[0] pin of FPGA

Hi, I wonder how to handle the DCLK and DATA[0] pin of FPGA. a. The datasheet says that these pins must be pulled high or low after configuration for JTAG mode(can't folat). b. However, the datash...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

The datasheet mention on connecting it to high or low when you are using JTAG mode only. So if you are using both JTAG and AS configuration mode then you do not need to weak-pull up it.

The internal weak-pull up on the DCLK pin will depends on your Quartus setting after entering usermode. Before entering usermode the DCLK pin will have weakpull-up active. No weakpull up on DATA0 pin.