Problems with DEV_CLRN and PINs, MAX10

@FvM

Thank you very much for your response. I recognise that I feel a little bit confused with all the configuration pins that are used in our design. I show you the schematic we have for our FPGA.

The pins that are rounded with red colour go/come to/from MCU. As you can see, we route the pins of CONF_DONE, nSTATUS (THAT WE ARE NOT USING), DEV_CLRn (pin 121) (routed to the MCU as an output from MCU and input to FPGA and USED). Also, we use the DEV_OE as an input from the power up device we use to feed the electronic components. Currently we are using DEV_OE as USER pin input but I'm not sure if I should use it as DEV_OE predetermined function.

I would very pleased if you could help me with this issue. Basically what I'm doing with this FPGA is obtaining PWM signals from a microcontroller (red ring from pins 38-58) and then I have designed some VHDL instances to process those signals (only if I input pin of ENABLE pwm from MCU is high) and make the PWM pulses to have a minimum pulse and dead time (IT's used for three-phase inverters to not short-circuit the bus). In order to detect a short-circuit from the semiconductors I obtain some feedback signals (green rings) from the drivers of the semiconductors that I compare with the PWM processed signals that I have triggered and I output(green rings) that I compare in a "error" designed instance and I give an error to the MCU though the pin 17. The output signals of processed PWM goes to TX of fiber optics and the feedback comes from RX of fiber optics.

When I have tested the design I have seen that the "error" instance gives me an error of all the PWM signals when I write the DEV_CLRn signal from MCU to FPGA the output signals (in tri-state) have an small distrubance (I don't remmember the voltage but maybe like 200-300mV but they are in tri-state) that I guess that makes the error instance to recognise a rising/falling edge (what I used to detect errors) and because I'm not getting anything from feedback, I give an error. Then I clear it and this error doesn't appear anymore, only when the DEV_CLRn is given.

What I would like to implement is the following:

1. When the MCU and FPGA is before and during powering up, the outputs that goes to the TX fiber optics must have a value that does not trigget the IGBTs so I would need that the output be forced to 0 when the FPGA is not even getting the DEV_CLRn from the MCU and then, before I enable the PWM from the input pin.
2. Help me with the policy I must follow to ensure the different CLR_N of the project. Now, when the PCB is powered up, the power up pin 122 goes to the FPGA but it's used as user refined (I have put it in the design as condition to trigger the pulses but I'm not sure about this position). Then, when the DEV_CLRn is written to High is when the program from .pof is loaded to the registers and starts working the FPGA but I obtain that initial error in all the pulses. Then I have a user-defined pin that enters the design and clears the different instances

I would apprecite if you could give me a feedback about the policy I'am following and the source of the error I obtain at the DEV_CLRn. I will continue to make some changes during this end of week and next one so I will be informing you.

Have a nice day,

Pedro