problem with the data transmitted from ethernet

I assume you have the user's guide for the board. I think you're referring to this board:

ftp://ftp.altera.com/outgoing/devkit/cycloneiii_3c120_dev_kit-v9.0.2.exe

The board uses a Marvell 88E111 10/100/1000 ethernet PHY. This uses a GMII interfaces. Looking at the example projects, these are the corresponding pins:

// ethernet interface

enet_mdc, // mdio clock

enet_mdio, // mdio data

enet_rx_clk, // receive clock

enet_tx_en, // transmit enable

enet_gtx_clk, // 125MHz transmit clock (for gigabit)

enet_rxd, // receive data

enet_txd, // transmit data

enet_rx_dv, // receive data valid

enet_resetn // reset (negated)

Jake

Thank you Jake! So the pin i mentioned like fsa is of no use if i want to access the data?

Another problem is that why the enet_rxd/enet_txd is a [3:0] one? that means the data is stucked at a 4 bit width?

I must make a correction. It appears that on your board, the pins are connected to the RGMII interface of the PHY. The difference being that the interface runs at double-data rate. So while the data bus in either direction is 4 bits, data is transferred on both edges of the clock producing 8 bits per clock.

If you intend to interface with the ethernet PHY, you really ought to consider using an ethernet MAC like the Altera Triple-Speed Ethernet MAC. If nothing else, you ought to read over it's documentation so as to understand the interface.

http://www.altera.com/literature/ug/ug_ethernet.pdf

Jake