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Altera_Forum
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13 years ago

problem with ssram on DE4 board

hi. I am trying to write a simple VHDL code to write some data to the ssram on the DE4 board and read it back. it is not optimized at all but serves the purpose. the project is running at ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Hi Cris72.

Thanks for your attention and reply.

About the read and write signals, they are driven from the topModule for just 1 clock for each read or write access.

And I have seen the datasheet of ssram. it is pipelined 1M*16bit from ISSI. there is nothing stated about the extra wait states. It is very odd but extra wait states worked when using higher frequency's while there is nothing about it in the datasheet !

Thanks for your time.