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Altera_Forum
Honored Contributor
Honored Contributorproblem with ssram on DE4 board
hi. I am trying to write a simple VHDL code to write some data to the ssram on the DE4 board and read it back. it is not optimized at all but serves the purpose. the project is running at ...
Altera_ForumHonored Contributor
Honored ContributorFirst of all consider your ssram timing specifications: you may need to add more waitstates (especially on reads) when you increase clock frequency.
Remark: I see that in your code you never deassert read and write signals, except on reset; this probably doesn't matter for your current purposes, but it's not correct.
