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hon1's avatar
hon1
Icon for New Contributor rankNew Contributor
2 years ago

Problem running MAX 10 - Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example

Hi, I tried to run the example (MAX 10 - Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example (intel.com)) on Quartus 18.0. When I generate HDL using Platform designer, I gotten the...
Fpga Devkit
ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi hlsleck,


I try run the example design that you mentioned by using 18.0 std. The design was compiled successfully and there is no error message from my side.


Can you share your .qar file? So that I can try debug the issue from my side.


Best regards,

Zi Ying