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wlin25's avatar
wlin25
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7 years ago

Problem of running HardwareLib example project on DE1-SoC

Hello, I used Cyclone V SoCKit (DE1-SoC) and the EDS version is 18.0. I tried to run the example project - Altera-SoCFPGA-HardwareLib-FPGA-CV-ARMCC. I follow the step of Bare Metal User Guide (se...
YauWai_G_Intel's avatar
YauWai_G_Intel
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7 years ago

From your report, it seems like the program execution was halted during the preloader (spl) and it enters the error loop. This usually could be failing to bring up the DDR memory or configuring the clock sources properly. Did you configure the board with the correct reference hardware design?

You can set a breakpoint in the spl code at the right spot before it enter the error dead loop, and debug step to see what is the actual failure in the preloader boot-up, which eventually caused the baremetal failed to run.​