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Altera_Forum
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10 years ago

Problem Implementing clock in Cyclone II (Altera-DE2)

Hello, I want to generate a clock with 50% duty cycle, but the frequency must be 9999 Hz <= f < 10000 Hz. I tried implementing with counter division and multiplication, but can't seem to find the ...
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Altera_Forum
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10 years ago

If you insist for two PLL then you need to use external path in Cyclone II...

you can use one prescaler to create input clock for PLL