Problem erasing EPCQ flash memory on INTEL Cyclone evaluation board with Generic Serial Flash Interface Intel running on NIOS II

Hi,

May I know which Cyclone Series are you referring to and what is the Quartus version are you using? Could you also provide the step used?

Hi,

the part number of the FPGA on INTEL evaluation board is "10CL025YU256" and the QUARTUS PROGRAMMER version is 18.1.1.

The operation sequence to erase a sector from my code is:

- ENABLES write operation (operation Code: 0x06)

- SEND erase command (OC: 0xD8 for "sector" erase)

- WAIT for WIP flag clear reading status register (OC: 0x05)

- DISABLES write command (OC: 0x04)

Note that the partial erase mentioned in the previous mail, is not true because it was due to a wrong read in ECLIPSE: the erase operation alway has no effects on the current sector.

Thanks a lot

Maurizio

Hi Maurizio,

May I know what is the clk frequency and setting used? Have you tried the design from https://fpgacloud.intel.com/devstore/platform/18.0.0/Standard/generic-serial-flash-interface-intel-fpga-ip-core-reference-design/https://fpgacloud.intel.com/devstore/platform/18.0.0/Standard/generic-serial-flash-interface-intel-fpga-ip-core-reference-design/?

Hi,

yes I tried the suggestions mentioned in the link, and the FPGA and the peripheral are clocked at 75MHz while the SPI clock to memory is about 5MHz (CLKDIV = 0x10)

All other parameters are on default value.

Thank you

Maurizio

Hi,

Could you share with me your Quartus design?

Hi,

do you have en e-mail where I can send it?

So, if you need I can share also the FW

Maurizio

Hi,

Please private message me with the FW.

Hi John,

just sent a private message: please confirm when received.

Thank you

Maurizio

Hi,

I have received the file and will take a look on this.

Hi,

From the project file provided you are using Quartus 18.1.1 Lite edition. May I know if you have Quartus license?