problam with modelsim

Hi Matan,

From what I see, you are using different package other that std logic between component and entity declaration result in mismatch type. Try to change you code in your testbench in component port same to std logic package

entity one_cnt is

port( serial_bit_input : in std_logic_vector (31 downto 0);

result : out integer range 0 to 32) ;

Refer to link below as it same case with you for reference

https://forums.intel.com/s/question/0D50P00003yyQfgSAE/modelsim-types-do-not-match?language=en_US

Thanks,

Regards