MShim18
New Contributor
New Contributorproblam with modelsim
the program supposed to count the number of '1' in a given 32bit input
library IEEE;
use IEEE.std_logic_1164.all;
entity one_cnt is
port( serial_bit_input : in std_logic_vector (31 downto 0);
result : out integer range 0 to 32) ;
end;
architecture behave of one_cnt is
signal cnt : integer range 0 to 32;
begin
process(serial_bit_input)
begin
cnt<=0;
count_loop : for i in 31 downto 0 loop
if serial_bit_input(i)='1' then
cnt<=cnt+1;
end if;
end loop count_loop;
result<=cnt;
end process;
end architecture;
as you can see :
* Fatal: (vsim-3807) Types do not match between component and entity for port "result"
what sould i do?
