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ChetanKarkera's avatar
ChetanKarkera
Icon for New Contributor rankNew Contributor
2 years ago

Power up and down sequencing for MAX 10 Devices

Hello,

Could you please confirm whether power sequencing is required for Max10 FPGAs?

While most related documents indicate that it is acceptable not to use power sequencing, there is one design guideline document that suggests the use of power sequencing for improved reliability.

" Design power sequencing and voltage regulators for the best device reliability—
although power sequencing is not required for correct operation, consider the
power-up timing of each rail to prevent problems with long-term device reliability
if you are designing a multi-rail powered system."

https://cdrdv2-public.intel.com/666778/m10_guidelines-683196-666778.pdf

Board Debug

2 Replies

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Please be advised that due to the absence of a response from you regarding the previous notification we provided, we will be transitioning this thread to community support. If you have any new questions or concerns, we kindly suggest opening a new thread to receive assistance from Intel experts. However, if you do not have any further inquiries, the community users will be available to assist you on this thread. Thank you for your understanding.