New Contributor
Super ContributorHi,
Do you mean that you have created your own new component IP QSYS module in Platform Designer and that custom IP has an PLL IP core inside?
When creating new component IP, will need to add the Synthesis Files for analyzed right? Usually PLL IP core will have a .qip file to include all the file sets but this .qip file can't be analyzed by component editor. Probably this cause the problem. Why not you just setup the PLL IP as an independent QSYS module and then make necessary connection to your own created QSYS module IP in Platform Designer.
Thanks,
Best Regards,
Sheng
New ContributorHi,
Yes, you are right. It exactly I have done and wanted to be sure that is not good way to use PLL inside qsys component.
Thanks for your answer.
