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sisa's avatar
sisa
Icon for New Contributor rankNew Contributor
7 years ago

Please, help me to correct verilog module for alarm temperature

module alarmsystem(clr,clk,alarm,CT,WT,Display); input clk,clr; input [31:0]CT; input [31:0]WT; output alarm; output [31:0]Display; wire reg_ld1,reg_ld2,reg_ld3,reg_ld4,reg_ld5; wire reg_clr1,...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi sisa,

I could able to compile & simulate the design provided over here.

please find the attachments for schematic & simulation results.

Try to compile & simulate at your end & provide specific error/issue if you have.

Regards,

Vikas Jathar