Forum Discussion
sisa
New Contributor
New ContributorPlease, help me to correct verilog module for alarm temperature
module alarmsystem(clr,clk,alarm,CT,WT,Display); input clk,clr; input [31:0]CT; input [31:0]WT; output alarm; output [31:0]Display; wire reg_ld1,reg_ld2,reg_ld3,reg_ld4,reg_ld5; wire reg_clr1,...
Vicky1
Regular Contributor
Regular ContributorHi,
Have you performed simulation? if not, try to write testbench for the design & check the simulation result.
refer the below old thread for testbench,
https://forums.intel.com/s/question/0D50P00004AbjLrSAJ/creating-test-bench-code-on-quartus-prime
Please provide bit more information about error/issue you have, if possible provide screenshot of waveform window.
Regards,
Vikas
sisaNew Contributor
New Contributori had a problem that my load input not connected to reg_ld...can u help me? 0166801697 this is my phone number.
