Occasional Contributor
Occasional ContributorDear Community,
I have learned a lot from your help, but I'm left with unresolved issues:
And there are still three nodes whose signals are not PIPE simulation only nodes and and yet their pinning is not described in the cv-avmm-manual:
I would be very happy if someone had an idea about this.
Occasional ContributorGot a little further:
1. Avalon MM Reference Design is a Qsys Design, so I could remove Pin-Out-signals
a) by removing it from the Export column or
b) by generating a Top-Level-Unit from within the Pin Planner for the qip-file, then instantiate the qip file in the Top-Level-Unit and comment out unwanted Out-Pins.
c) Also I found a possibility to delete Pins in the Pin Planner using the context menu of the pin.
2. For default pin configuration I found:
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
in the corresponding Golden Reference Design qsf file.
Hope this is correct and sufficient not to damage the board.
3. For pcie_cv_hip_avmm_0_npor_npor I generated a signal by ORing perst and nreset as described here:
npor <= pcie_cv_hip_avmm_0_npor_pin_perst or reset_reset_n;
and assigning it to the port in the Top-Level-Unit-Instantiation. Hope that is correct.
For: dut_reconfig_busy_reconfig_busy (input), pcie_cv_hip_avmm_0_reconfig_clk_locked_fixedclk_locked, still no idea.
I have commented it out in the Top-Level-Unit for now.
