Occasional Contributor
Super ContributorUse the View menu options, the Pin Finder, and pin tooltips (hover over a pin) to see these right in the tool. The Pin Legend will help.
If you still need it, just search for a device pinout on the Intel web site.
Occasional ContributorAh, I see! Great!
I also found some Pin Description in the "Cyclone V GT FPGA Development Board. Reference Manual.
But there seem to be lots of inputs and outputs in the CV Avalon-MM Interface for PCIe Solutions User Guide's ep_g1x4-entity intended only for simulation.
For instance: PIPE Interface Signals
These PIPE signals are available for Gen1 and Gen2 variants so that you can simulate using either the
serial or the PIPE interface. Simulation is much faster using the PIPE interface because the PIPE
simulation bypasses the SERDES model . By default, the PIPE interface is 8 bits for Gen1 and Gen2. You
can use the PIPE interface for simulation even though your actual design includes a serial interface to the
internal transceivers. However, it is not possible to use the Hard IP PIPE interface in hardware, including
probing these signals using SignalTap® II Embedded Logic Analyzer.(p.30)
Is there a way to tell the Pin Planner that a pin is not used - without removing ist from the vhdl-entity ports list?
