Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- maybe HDL embedded I/O assignments? at least you don't have to open the .qsf --- Quote End --- Open a .qsf? Never use 'em, not on purpose anyway ;) My design process involves checking all code and a Tcl synthesis, timing, and simulation scripts into CVS. The Quartus Tcl script creates a tool-version specific build directory, and then all generated files go there. If I have to change a setting and I'm too lazy to look up the corresponding Tcl command, I'll use the Quartus GUI, generate a Tcl file for the project, and extract the appropriate Tcl commands and put them in my script. Similarly, I'll use the TimeQuest GUI to figure out what to put in my .sdc script. When done, I blow away all the Quartus build chaff. The nice thing about this approach is that its worked since MAX+PLUS II, and I never have to convert a project from one version of Quartus to the next. If I was to use embedded HDL I/O assignments, I think the top-level entities would start to look pretty darn ugly, and I really hate repeating myself ... I can live with copying and pasting the entity definition, but copying a bunch of embedded HDL assignments would be too much :) Having to comment out the transceiver pins annoys me, as it is a stupid decision to make in the synthesis tool. When a pin is unused in the design (and set to 0, 1, or Z), the synthesis tool can detect that, and then do whatever it is doing now (when the pin does not exist in the design). Of course, perhaps I'm just being grumpy :) Cheers, Dave