Pin Assignments -- less tedious way?

Hi thepancake,

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i also to try and use a single pinout for a board and use port mapping at the top level to make the "assignments"

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Here's a question for you; what do you do with designs that contain transceivers?

I'm working with the Stratix IV GX development kit, and I find it annoying that I can only have a top-level design with the transceiver and reference clock pins defined if they are actually connected to a transceiver block. This means I have to comment out the top-level entity pins for designs that do not use transceivers. I still leave the constraints in the design for those pins, but then I get ignored constraints warnings.

If I just have to 'live with this', then I was going to look into splitting the synthesis process into an elaboration phase, extract the pin names actually used in a design, and then go through my constraints list of all pins, and only apply those constraints that have actual pins in the design. Then finish the P&R process. I think this should work (though I have not tested it). This would at least eliminate the ignored assignments warnings.

With this scheme, I'd have constraints Tcl procedures that would be common to a specific board design (the GX development kit), but I'd have top-level entities that could be design-specific (include/exclude transceiver channels).

Any recommendations?

Cheers,

Dave