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I exported the assignments from "Assignment Editor" for an example project, and it looks like it's just a Tcl script. I looked through your attached files, and I imagine that at some point you had to reference the schematic and enter each pin manually. Is that correct?
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The way I generate the files is to either start with a schematic, or start with an example design and export the pin assignments. The Altera constraints are waste of typing, so in constraints.tcl I use a short-hand "keyword=value" notation for the pin assignments and constraints, and then use Tcl loops to convert the keywords and values to Altera-specific Tcl constraints.
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I know it's a one-time ordeal, but I was wondering if these assignments already existed. Particularly, it's confusing to go between the two schematics: the schematic for the HSMC card, and then the schematic for the development board.
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I always use the same design pin names (entity definition) for the top-level file, with all pins defined (regardless of whether the design uses them or not). For example, the HSMC connector would be generically named hsma_lvds_a etc. What those pins connect to is design-dependent and happens inside the top-level design file, i.e., hsma_lvds_a will get renamed or aliased to make the code easier to read.
Try not to rename top-level pins to match an HDL design, as then you have to have a constraints file that depends on your design. Keep the top-level entity pin names the same, and simply connect them to new names at the top-level file in a project.
Cheers,
Dave
Honored Contributor
