Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

PCIE interface fails in Cyclone IV GX DevKit

I have configured the FPGA Cyclone IV GX (Cyclone IV GX Dev Kit) with PCIE firmware example from this site: http://www.alterawiki.com/wiki/pci_express_in_qsys_example_designs The cpld and flash me...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Bob, thank you for your response.

The external reset is deasserted to high state. The ref_clk signal from PC was analyzed with oscilloscope and is ok too.

The core_clk_out is not being generated from the ip core.

Someone could be suggest how to test if the PCI IP on FPGA is alive?

Thank you