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Honored Contributor
Honored ContributorPCIe Hard IP returning stale data for Cyclone IV
I have recently ported a PCIe endpoint design working on Arria V to Cyclone IV , ( Transciever Starter Kit ) . I need to go back but don't believe I see the problem on Arria V which is a very ...
Altera_ForumHonored Contributor
Honored ContributorI wonder if the PCIe to Avalon bridge (for PCIe slave cycles) actually has two separate Avalon master interfaces, one for reads and one for writes?
That might allow a read transfer to overtake a write one - even though the PCIe master shouldn't have requested the read until after it has seen the completion message for the write.
